Priority Interrupt : PRIORITY BASED DATA TRANSFER IN CPU : Daisy Chaining Method

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In this Lecture you will learn about the concept of Priority Interrupt or Daisy Chaining Method in Computer Architecture. How data are transferred between Input output device to memory without involving of CPU.. Definition : Data transfer between CPU and I/O device is initiated by CPU. However cpu can't start the data transfer unless the device is ready to communicate with the cpu. "The readiness of the device can be determine from an Interrupt signal". "A Priority Interrupt is a system that determine a 'priority' over various sources to decide which condition is to be execute firstly when two or more request arrive simultaneously". Method for Priority Interrupt: Daisy-Chaining Method : It is a serial connection of Interrupt lines. It consist of a serial connection of all devices that request an Interrupt. The device with highest priority placed in 1st Position and lowest priority placed on 2nd position for execution. Working: The cpu responds to an interrupt request by enabling the INTACK (interrupt acknowledge) line. This signal is received by device 1 at its PI (priority Input), the acknowledge signal passes on the next device through PO (priority output) only if device1 is not requesting an interrupt. If device1 has pending interrupt, it blocks the acknowledge signal from the next device by passing a 0 in the PO output. It then proceeds to insert its own interrupt vector address (VAD) into the data bus for the cpu to use during the interrupt cycle. If device does not have pending interrupts, it transmits the acknowledge signal to the next device by placing a 1 in its PO output. Thus the device with PI=1 and PO=0 is the one with the highest priority. This method gives the highest priority to the device that receives an interrupt acknowledge signal from CPU. VAD: Vector address provides the ISR(interrupt service request) to the processor for interrupt execution . A memory address to which processor vectors (transfers into program counter of 8086) a new address on an interrupt for servicing that interrupt. for more videos subscribe the channel : Computer science academy by Dinesh Sir